Design and Implementation of a Standard Cell Library for Building Asynchronous ASICs - Moreira, Matheus Trevisan (Revista da Graduação, 2011)
Asynchronous ASIC design automation tools and standard cell libraries development lag behind their synchronous counterpart. Therefore, most asynchronous designs still make use of full-custom design approaches, which contributes to make asynchronous circuits less used. To help in solving this problem this work presents the design and implementation of a standard cell library for building asynchronous application specific integrated circuits (ASICs), called ASCEnD-ST65 (currently at version 0.1), developed for a 65nm gate length STMicroelectronics CMOS process. An abridged version of this library was designed to implement an asynchronous network on chip (NoC) router. Nevertheless, those cells presented elevated leakage power consumption. This characteristic was treated in ASCEnD-ST65, by proposing a new, robust design flow. This flow contains a novel method to determine the dimension of transistors in the CMOS implementation of C-Element gates, fundamental elements in asynchronous design. This work presents the details of the method and adopts it throughout the specification of the library cells. The designed standard cells count with several views: layout, schematic, symbol, Verilog and abstract. LEF and LIB files describe the physical and electrical characteristics for each cell, and the cells have been characterized for three different process corners, worst, typical and best cases. A total of 251 cells were designed. Among these are a large amount of implementations and variations of C-Elements, the main gate used in many asynchronous design styles. A tradeoff between three different C-Element CMOS implementations – Conventional, Symmetric and Weak Feedback – is presented in this work. Also, the library contains other cells, such as metastability filters. To validate the library, two different IC design flows were adopted. First, a typical flow consisting of VHDL sources synthesized and implemented through the Cadence Framework was used to generate and simulate an asynchronous NoC router. Next, a novel design flow, consisting of a Balsa description synthesized through the Teak System was used to generate the netlist of an asynchronous RSA based cryptography circuit. The layout of this circuit was obtained through Cadence Encounter and simulated through Spectre. The results prove the successful integration of this library and Teak System.